About the role
AI summarisedJoin the AMD SerDes Technology Group to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. This role involves hands-on analog/mixed-signal layout design contributing to the future connectivity of AMD CPU and GPU products.
FablessOnsiteEngineering
Key Responsibilities
- Layout design of high speed and high performance SerDes analog mixed signal circuits according to project requirements.
- Performing block-level physical implementation including floor-planning, power distribution network design, and clock/signal routing.
- Executing analog and mixed-signal transistor level layout.
- Participating in post-layout circuit performance analysis.
- Contributing to block, IP, and chip level integration activities.
- Estimating realistic schedules, tracking progress, and reporting status clearly.
- Driving layout productivity improvement initiatives, such as pcell development and automation.
Requirements
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related field.
- Passion for high-speed layout design with innovative problem-solving approaches.
- Strong analytical and problem-solving abilities.
- Experience collaborating with engineers across different sites and time zones.
- Proficiency in analog/mixed-signal layout fundamentals (IR, EM, capacitances, RC delay).
- Strong in physical design verifications (LVS, DRC, ERC, ANT, ESD, etc.).