About the role

AI summarised

Staff Analog Layout Engineer at Marvell, a semiconductor company. Responsible for running simulations and verifications using Cadence Virtuoso, collaborating with designers to refine designs, and owning the full development cycle from floorplan to delivery. Requires fundamental understanding of electrical concepts and experience with high-speed or precision analog circuits.

FablessFull-timeGeneral

Key Responsibilities

Run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications.
Participate in routine meetings as a technical mentor, layout team, and the broader project team, providing updates on progress and presenting specific issues or solutions encountered during development.
Assume more responsibility and ownership of tasks, from cells to functional blocks, to higher-level macros, to full interfaces or chips.
Have ownership through the full development cycle: floorplan, layout, verification, delivery, and support.
Collaborate with global teams across Argentina, Singapore, the U.S., and Europe.

Requirements

Have fundamental understanding of electrical concepts, likely acquired through a degree in Electrical Engineering (graduate or undergraduate).
Know how to use CAD tools to do the implementation layers, microelectronic layers in design that go beyond the schematics.
Track record of delivering high-speed or precision analog circuits, preferably in multiple process nodes.
Have excellent communication skills to give status updates to your team, present to global teams in different time zones, and to share information with many different levels of personnel at Marvell.