About the role

AI summarised

The Senior Staff Engineer, Hardware & Silicon Validation at Marvell leads PHY validation for storage devices in a post-silicon environment. This role involves defining and executing validation plans, performing high-speed signal analysis, debugging PHY protocol issues, and collaborating with cross-functional teams and customers to resolve technical challenges. The position requires deep expertise in high-speed interfaces, SERDES testing, and lab-based validation using advanced test equipment.

FablessOnsite

Key Responsibilities

Complete responsibility of PHY Validation in post-silicon environment
Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices
Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER
Analyze and debug issues on Phy protocol of storage interface (SATA, SAS, PCIe, Ethernet)
Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers
Lead collaborative technical discussions to drive resolution on technical issues
Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Ethernet/PCIe PHY
Work closely with customers to address design issue and debug failure cases

Requirements

Bachelor of Science in Electrical Engineering with 8-10 years of relevant work experience, or Master of Science in Electrical Engineering with 6-8 years of relevant work experience preferred
Strong understanding of high-speed SERDES, equalization technique and any high-speed standard (IEEE802.3, PCIe, DP, etc.)
Proven experience in High-Speed IO testing, debugging and validation, strong lab skills with hands on experience, in system bring up, system testing and debug
In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.)
Working knowledge of IEEE 802.3 400G/800G/1.6T interface and characterization
Working knowledge of board design; able to read board schematics and board layout
Knowledge in SERDES modeling techniques and proven experience working with Perl or Python
Working knowledge and experience on PCIe and/or SAS/SATA SERDES and extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is a definite plus