About the role
AI summarisedThe focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s SERDES IP, resulting in no bugs in the final design.
FablessOnsiteEngineering
Key Responsibilities
- Circuit design of wireline transceiver building blocks (PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.).
- Conduct peer reviews of circuit design and verification results.
- Working with validation team to evaluate silicon results.
Requirements
- Deep understanding of analog design.
- Ability to lead, attend, and present at design review meetings with worldwide teams.
- Bachelors/Masters/Phd Degree in Electronic Engineering.