About the role

AI summarised

The Foundation IP Design Engineer will join a memory design team to develop memory compilers and custom macros at the transistor level. Responsibilities include analyzing memory architectures, designing and simulating circuit blocks, performing post-layout verification, integrating characterization flows, automating scripts, specifying memory models, documenting designs, defining silicon test plans, and debugging silicon issues. The role requires strong analog/digital circuit knowledge, scripting ability, and collaboration skills.

FablessOnsite

Key Responsibilities

Analyze different memory architectures and highlight the tradeoffs
Design and build memory or circuit blocks at the gate or transistor level
Simulate and analyze the circuit design using transistor level simulators
Extract the layout and perform post-layout simulations and verification
Floorplan physical implementation and leafcell layout integration to build the physical macro
Integrate characterization flow to extract timing and power information
Develop scripts to automate characterization flow, simulations, and verification
Specify and verify various behavioral and physical memory models
Document the design specifications, behavioral description, and timing diagrams
Specify silicon test plan and correlate silicon to simulation data

Requirements

Knowledge in development of memory compilers or custom digital circuits of all types; SRAMs, Register-files, Multi-ports, ROM, etc…
Good understanding of transistor level circuit behavior and device physics
Good understanding of signal integrity, EM/IR, and reliability analysis
Understanding of memory behavioral and physical models
Understanding of DFT schemes and chip level integration
Familiarity with test setups, silicon testing and debug is a plus
Proficient in running simulators, writing automation scripts, and are tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven and good at multi-tasking
Requires a BS in Electrical Engineering and 5+ years of related experience