About the role
AI summarisedThis Senior/Lead Research Engineer role focuses on owning and optimizing wafer-level bonding processes such as hybrid bonding and TBDB. The position involves establishing SPC strategies, driving yield improvement through statistical analysis, and managing tool recipes to enable advanced packaging and 3DIC technologies.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- Own and maintain SPC control strategies for bonding processes across multiple toolsets.
- Define Critical Process Parameters (CPPs) and Critical Quality Attributes (CQAs) such as alignment accuracy, bond strength, and defectivity.
- Establish and optimize control limits, reaction plans, and process windows to ensure process robustness.
- Drive yield enhancement through structured data analytics, statistical modeling, DOE, and correlation studies.
- Lead root-cause investigations for issues such as voids, delamination, alignment offsets, and particle-induced defects.
- Execute tool health monitoring, run-to-run control, and equipment baseline management.
- Diagnose complex process failures involving void formation, debonding, overlay/registration errors, and thermal mismatch.
- Develop and maintain comprehensive documentation including SOPs, Control Plans, and OCAPs.
Requirements
- Bachelor's degree in Materials Science, Chemical, Mechanical, Electrical Engineering, or related fields.
- 3+ years of hands-on experience in wafer bonding, advanced packaging, 3D integration, or related semiconductor process engineering.
- Practical experience with hybrid wafer bonding, direct bonding, and/or Temporary Bonding & Debonding (TBDB) equipment.
- Familiarity with bonding-related metrology such as IR inspection, SAM, profilometry, and bond-strength measurement.
- Knowledge of overlay/alignment metrology and thickness mapping.
- Strong command of SPC, process control methodology, statistical data analysis, and DOE.
- Proficiency in problem-solving frameworks such as 8D and FMEA.
- Understanding of 3DIC, chiplets, hybrid bonding, and advanced packaging process flows.
- Experience with HVM tools, bonding chemistry, plasma activation, and surface conditioning.
- Knowledge of thermal and mechanical behavior of bonded wafer stacks.