About the role

AI summarised

The Layout Engineer will work within the Library Group of Central Engineering Group, focusing on circuit design for memory, I/O, and standard cells. Responsibilities include creating quality layouts, performing physical verifications, managing layout floor-planning and scheduling, and contributing to layout methodology documentation. The role requires strong layout knowledge in submicron processes and experience with Cadence and verification tools, with opportunities to lead junior engineers and contribute to technology reviews.

FablessOnsite

Key Responsibilities

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
Schedule time-line & layout floor-planning
Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
Able to lead or train a team of junior engineers
Good leadership quality on project management

Requirements

Strong layout knowledge with a minimum of 2 to 3 years of experience
Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools
Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm, 2nm etc
Experienced in digital (standard cell, memory, I/O) layout
Experienced in analog layout is also a plus
Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process
Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools
Good experience in Floor-planning, hierarchy layout and chip integration
Knowledge of Script Programming and SKILL Programming would be a plus
Good knowledge on memory layout topology
Experience in memory compiler will be a plus
Self-reliant, with ability to work independently as well as a team