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A*STAR

Senior Scientist (C2W bonding), (HI), IME

A*STAR
ResearchSingaporeFull-time2 days ago
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About the role

AI summarised

Senior Scientist role at IME focusing on chip-to-wafer (C2W) bonding and advanced packaging in semiconductor R&D. The position involves leading process development, NPI to HVM ramp, and collaborating on cutting-edge heterogeneous integration projects.

ResearchFull-timeInstitute of Microelectronics

Key Responsibilities

  • The opportunity to work on cutting-edge research projects in advanced packaging and heterogeneous integration.
  • A collaborative & interdisciplinary work environment and access to state-of-the-art facilities and resources.
  • File intellectual property (IP) promptly for new research findings.
  • Publish research in peer-reviewed journals and present findings at international conferences.
  • Researchers have access to advanced laboratories and characterisation equipment, fostering innovation and enabling the development of groundbreaking technologies. The institute encourages interdisciplinary collaboration and offers opportunities for professional growth and development.

Requirements

  • PhD in Materials Science & Engineering, Mechanical, Chemical, Electronics/ Electrical & Computer Engineering, Physics, Chemistry or a closely related field.
  • 5-10 years of experience in the semiconductor industry, with expertise in package assembly processes and exposure to advanced package assembly technologies such as thermal compression bonding, chip-to-wafer bonding, underfilling, etc.
  • Broad hands-on knowledge of one or more unit processes—such as wafer thinning, dicing, flip chip bonding, underfilling, solder ball attachment, wafer-level compression moulding - is preferred.
  • Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments.
  • Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab).
  • NPI to HVM ramp experience: process window definition, control plans, and yield/cost improvement through pilot to high-volume manufacturing (foundry/OSAT).
  • Reliability & standards: working knowledge of JEDEC/IPC/JESD (e.g., HTS, TC, HAST, BLR, EM), and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX).
  • Excellent written and verbal communication abilities.
  • Demonstrated ability to manage multiple projects and priorities in a research and translational environment.
  • Able to work effectively with multi-ethnic, multicultural teams and to build inclusive, high-performing teams.
  • Proven ability to author impactful conference/journal papers and deliver presentations at international conferences (e.g., ECTC, IEDM, VLSI Symposia) across North America, Europe, and Asia.