About the role
AI summarisedJoin our Library Group within the Central Engineering Group to focus on circuit design for memory, I/O (Input/Output), and Standard Cells. We are seeking experienced Layout Engineers to contribute to high-quality physical implementations in advanced submicron processes.
FablessOnsite
Key Responsibilities
- Scheduling timelines and performing layout floor-planning.
- Completing quality layouts and verifications within the planned schedule.
- Contributing to memory layout design and physical verifications including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS process.
- Leading new technology reviews to compile documentation on layout methodology, flow, and guidelines.
Requirements
- Minimum of 2 to 3 years of strong layout experience.
- Strong layout knowledge in submicron processes (e.g., 16nm, 7nm, 5nm, 3nm, 2nm).
- Experienced in digital layout (standard cell, memory, I/O).
- Proficiency in Cadence layout and schematic capture.
- Familiarity with CALIBRE & Hercules verification tools.
- Ability to work independently and collaboratively within a team setting.