About the role

AI summarised

The NAND Design Rule Manager leads a team responsible for developing and maintaining design rules and process design kits (PDKs) for advanced 3D NAND technologies. This role involves coordinating with process integration, device, layout, modeling, and quality teams to ensure accurate design rule checks, timely issue resolution, and high-quality documentation across R&D and production. The manager drives continuous improvement in design-rule pathfinding and supports the full lifecycle of NAND product development.

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Key Responsibilities

Lead the release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments
Own program execution and achievements from kickoff through end-of-life
Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations
Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions
Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions
Build and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies
Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels
Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination
Drive continuous improvement in design-rule pathfinding and document takeaways that improve production parts still under development

Requirements

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master’s degree with 8+ years; or bachelor’s degree with 13+ years in the semiconductor industry (Process Integration, Yield Improvement, Product Engineering, Test Structure Development, or Unit Process Development)
Direct experience working with PDK, design rules, and layout, including small layout assignments, is necessary
Skilled in CAD software such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE or their equivalents
Solid understanding of semiconductor device physics and VLSI silicon processing and integration flow
Demonstrated ability to resolve complex issues and communicate clearly under pressure
Understanding of 3D NAND process flow and major NAND components (e.g., bit-line sensing, word-line driver, data path, and analog circuits)
Familiarity with CAD group interactions, data post-processing, and data transfer from built databases to reticles
Prior leadership experience in R&D for NAND or other memory technologies (preferred)