About the role

AI summarised

Device Engineer at STMicroelectronics, a global semiconductor company. Responsible for yield improvement, lot on hold reduction, and process robustness in a fab environment. Requires engineering degree and basic semiconductor knowledge.

IDMFull-timeDevice Engineering

Key Responsibilities

Monitor and improve Electrical Wafer Sort (EWS) Test Yield loss (translated to SFV) of the technology.
Monitor and reduce Parametric Testing (PT) & Electrical Wafer Sort (EWS) Test scraps by correctly identifying the root cause (process step/ equipment) and putting in place containment, corrective and preventive actions to avoid re-occurrence.
Daily management of lot on hold (inline, T84, EWS) with daily disposition; work with Manufacturing Quality Assurance (MQA), Division in carrying out MRB for timely NCL disposition.
Support Process/Module Engineers with Electrical Data Analysis for new tool qualification.
Drive process change qualification when marginality in the product or process is identified.
Work with Product Engineers in optimizing the sort test program and specification limits and Statistical Bin limits wherever applicable.
Work with Process Engineers, Division in improving Inline and PT CPK.
Work with Sending Plant, Division, RAT, Process Engineers and Production Control for techno / new product transfer qualifications.
Understand basic failure analysis and carry out bench measurement for root cause analysis.
Work with defectivity team in reducing inline defectivity for yield and quality improvement.
Support Customer Quality Assurance (CQA) in Customer Incidence (CI) analysis.
Involve in cost improvement projects.

Requirements

Degree in Engineering.
Basic Semiconductor knowledge.
Knowledge about Bench Analyzer operation is a plus.
Basic Statistics knowledge.
Good Team player.
Knowledge about Office application is a must.
Knowledge about Ace-Xp (EDA Tool) or JMP or Spotfire is an added advantage.