STAFF ENGINEER - HIG HBM PSE

Key Responsibilities

• Validation Execution Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment, ensuring on‑schedule starts/completions, risk‑aware re‑plans, and efficient material usage. Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time. Guarantee coverage completeness across MBIST and Native flows; drive Hot/Cold corners, TSV screen/AQLK, async timing boundary coverage, and evidence‑backed closure.
• Platform Leadership Develop and debug test programs on SM3/Cobra and Advantest V93K; enforce code quality, reviews, and release discipline. Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets.
• Advanced Analysis, Verilog Simulation & Automation Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes. Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment. Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.
• Debug & Continuous Improvement Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root‑cause evidence. Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning). Contribute to DFMEA gap closure and codify 'Definition of Success' for validation quality.
• Mentorship & Collaboration Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards. Partner with global teams (Boise, Folsom, Hyderabad, Taiwan) for material readiness and platform enablement.