About the role
AI summarisedSenior/Staff STPG Product Engineering (Probe) role at Micron, a semiconductor memory company. The engineer owns probe strategy and silicon learning at wafer test, from pre-silicon design-to-probe staging through high-volume manufacturing, driving yield, quality, and test-cost outcomes.
IDMFull-timeSTPG
Key Responsibilities
- Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard-bands.
- Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.
- Establish probe limits and guard-bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
- Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.
- Partner with Design, DFT, and DV teams during pre-silicon phases to drive effective design-to-probe staging.
- Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
- Support first-silicon bring-up using engineering probe platforms and lab-based characterization setups.
- Perform silicon and device-level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.
- Drive wafer-level yield learning, bin definitions, and failure-mode analysis at probe.
- Drive test efficiency improvements through coverage right-sizing and flow optimization, aligned to product and market needs.
Requirements
- Bachelor's, Master's degree, or PhD in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.
- Strong fundamentals in semiconductor devices, wafer test, and product engineering.
- Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.
- Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design-to-manufacturing integration.
- Strong analytical skills and ability to drive structured root-cause analysis.
- Effective communication skills and ability to work across global, cross-functional teams.
- Experience with NAND / memory products (preferred).
- Experience working directly with Design, Process Integration, or Device teams to resolve silicon or product issues (preferred).
- Exposure to probe flow optimization, yield learning, or test cost reduction (preferred).
- Familiarity with DFT verification, reliability screening, or test correlation methodologies (preferred).
- Experience with Python, SQL, JMP, or data / ML tools (preferred).
- Demonstrated ability to independently drive complex technical problems from concept through execution (preferred).
