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STMicroelectronics

Intern, IC Digital Design (Front-end)

STMicroelectronics
Integrated Device ManufacturingSingapore, SingaporeFull-time4 months ago
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About the role

AI summarised

This is a digital design internship at STMicroelectronics, a global semiconductor company. The intern will work on developing and automating design verification flows, including MBIST packaging, Spyglass CDC netlist setup, and front-end tasks like linting and CDC/RDC. The role requires strong fundamentals in digital logic design, proficiency in Verilog/SystemVerilog, and scripting skills in Python and other languages.

IDMFull-timeDigital Design Front-End

Key Responsibilities

  • Design and implement a new membox packaging flow for generic MBIST, ensuring modularity and reusability across different memory instances.
  • Collaborate with memory IP teams to understand requirements and optimize the packaging flow for efficiency and scalability.
  • Prepare Lint, CDC, and RDC verification tasks into a standalone kit.
  • Integrate and validate the recital flow within the design kit to ensure seamless operation and compliance with design standards.
  • Establish and configure a CDC netlist flow using Synopsys Spyglass to detect and analyze clock domain crossing issues.
  • Automate the generation and verification of CDC reports to support timely design sign-off.
  • Develop scripts and automation tools to streamline various digital design verification flows, improving productivity and reducing manual intervention.
  • Troubleshoot and debug flow issues, providing timely solutions to support design teams.
  • Work closely with cross-functional teams including design, verification, and EDA tool experts to align flow development with project goals.
  • Document processes, scripts, and flow configurations to ensure knowledge sharing and maintainability.

Requirements

  • Able to commit minimum 8 months of internship.
  • Pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Strong fundamentals in digital logic design, hardware design principles.
  • Proficiency in Verilog or SystemVerilog for digital design and verification.
  • Programming or scripting skills in Python, plus at least one of: C/C++, SystemVerilog, TCL, or Shell.
  • Familiarity with Synopsys tools such as Spyglass, Design Compiler, or similar linting and CDC analysis tools is highly desirable.
  • Ability to analyze technical data and generate concise reports.
  • Experience or coursework in VLSI/ASIC design or verification.
  • Exposure to formal verification, linting, or CDC tools.
  • Interest in EDA tool evaluation and design methodology research.
  • Strong curiosity about improving engineering workflows.
  • Good communication skills to collaborate effectively with cross-functional teams.
  • Self-motivated and eager to learn new tools, methodologies, and industry best practices.
  • Ability to work independently as well as in a team-oriented environment.