About the role
AI summarisedR&D engineer position focused on design and physical implementation of high-performance System-On-Chip ASICs at a semiconductor company. The role involves leading physical design teams, using EDA tools for 5nm/3nm/2nm process technologies, and collaborating with RTL and physical design teams to resolve timing violations.
FablessFull-timeGeneral
Key Responsibilities
- Working experience leading team in physical design implementation of large ASICs (500 to 800 million gates complexity).
- Demonstrated ability in providing technical support to customers and managing customer working relationship.
- Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
- In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
- Collaborating with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.
- Utilize commercial and in-house EDA tools for the design and implementation of 500 ~ 800 million gate integrated circuits in 5nm/3nm/2nm process technologies.
- Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products.
Requirements
- Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 7 years or more experience in a relevant field.
- Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity
- Strong analytical problem-solving skills and the ability to collaborate in cross-functional team environments
- Experience in Perl, Tcl & Python Scripting languages