VIS

Senior Engineer ( Yield Enhancement ) (Ref: 250900136)

VIS
Foundry OperationsSingaporeOnsitePosted 2 weeks ago

About the role

AI summarised

Drive defect reduction and yield improvement activities by liaising with module engineers, supervising technical operations, and performing in-depth failure analysis on high-volume manufacturing processes.

FoundryOnsiteIntegration

Key Responsibilities

  • Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation.
  • Operate FIB/SEM/EDX for inline failure analysis and perform defect characterization using process tools.
  • Perform partition analysis on defect sources and generate detailed reports on issues.
  • Track inline defect performance by layer/process tool/chamber on a weekly basis and perform killer ration analysis.
  • Build and develop defect source land tool’s defect source fingerprinting.
  • Liaise with process engineers across different modules to troubleshoot inline defects and drive reduction activities.
  • Provide scan support in low yield investigations and collaborate with PI/PE on technology enhancement activities.
  • Automate daily activities to improve team troubleshooting speed and maintain wafer quality compliance.

Requirements

  • Masters or Bachelor Degree in Electrical, Electronics, Chemical, or Material Science Engineering.
  • 2-8 years of relevant fab work experience in high volume manufacturing of electronics components or front end wafer fab industry.
  • Responsible for complying with and implementing EHSS system, policies, procedures, and guidelines.
  • Excellent interpersonal and communication skills with strong leadership capability.
  • Proven ability to work as a team player.