About the role

AI summarised

The Package Silicon Technology Node Development Director/DMTS provides technical leadership in developing chip package interaction technology roadmaps for advanced silicon technology node transitions in packaging. This role involves leading global technical silicon teams, collaborating with fab process integration, product and package design, and quality teams to ensure successful launches of future memory products. The position requires deep expertise in semiconductor processing, chip-package-interaction failure mechanisms, and proven ability to drive innovation through technical leadership and mentoring.

IDMOnsiteAssembly & Test

Key Responsibilities

Develop and communicate silicon technology roadmaps and working closely with multiple fab sites on advanced memory technology transitions
Collaborate with engineering teams in fab process integration, assembly design and development, product design and development engineering teams to establish CPI risk mitigation strategies
Regularly align priorities, timelines, and resource needs with management and stakeholders to keep silicon technology and test vehicles working seamlessly with design & process requirements

Requirements

Good understanding and experience with process technology development business processes and strategy
Understanding of memory technologies and processing preferred
semiconductor processing and devices
Expertise in chip-package-interaction failure mechanisms and risk assessments
Demonstrated ability to form collaborations (internal and external) and internal customers
Ability to work on multiple projects and work through cross-disciplinary and cross-organizational issues
Strong presentation skills and experience
Strong relationship building and matrix management skills
Proven ability to solicit feedback, accept input, and analyze success/failure of self and team
Master’s or Phd degree or higher in Materials Science/Engineering, Chemical Engineering, Electrical Engineering, Physics, Chemistry or a similar field is preferred
15+ years of proven experience in related fields
Experience with chip package interactions, semiconductor electrical/physical failure mechanisms, failure analysis, testing/screening methods, and reliability testing
Documented record of technical expertise and innovation resulting in high impact results; publications, patents; and track record of technical leadership and mentoring
Excellent communication skills with the ability to convey sophisticated technical concepts to both technical and non-technical partners