About the role
AI summarisedMid-level Process Engineer role in a Tier 1 IDM semiconductor fab, responsible for sustaining and improving wafer fab processes including CVD, PVD, Etch, CMP, and Lithography. Focus on yield enhancement, cost reduction, and process optimization using data-driven methodologies in an ISO 5 cleanroom environment.
IDMOnsite
Key Responsibilities
- Own and sustain multiple semiconductor process modules including CVD, PVD, Etch, CMP, and Lithography
- Drive yield improvement projects using statistical analysis and DOE methodologies
- Perform root cause analysis for process excursions and implement corrective actions
- Develop and optimize process recipes to meet device performance and reliability specifications
- Collaborate with equipment engineers to troubleshoot and improve tool performance
- Lead cross-functional teams for new process introductions and technology transfers
- Monitor process performance using SPC charts and implement control plans
- Generate and maintain process documentation including FMEAs, control plans, and standard operating procedures
- Support production ramp and capacity expansion activities
- Interface with integration and device teams to align process capabilities with product requirements
Requirements
- Bachelor's degree in Chemical Engineering, Materials Science, Electrical Engineering, or related field
- 3-7 years of semiconductor process engineering experience in a high-volume manufacturing environment
- Demonstrated experience with at least two process modules: CVD, PVD, Etch, CMP, or Lithography
- Strong statistical analysis skills using JMP, Minitab, or similar software
- Experience with DOE, SPC, and FMEA methodologies
- Six Sigma Green Belt certification required; Black Belt preferred
- Proficiency in SQL for data extraction and analysis
- Ability to work effectively in an ISO 5 cleanroom environment for extended periods
- Excellent problem-solving skills using structured methodologies like 8D or DMAIC
- Strong communication skills to present technical findings to cross-functional teams
- Experience with Applied Materials, Lam Research, or Tokyo Electron equipment preferred
- Knowledge of semiconductor device physics and failure analysis techniques
- Willingness to work flexible hours during process development or troubleshooting activities
- Legal authorization to work in the United States