About the role
AI summarisedThe Staff Engineer - HBM PSE role at Micron Technology involves leading end-to-end validation execution for high-bandwidth memory (HBM) products, developing and debugging test programs on platforms like SM3/Cobra and Advantest V93K, performing power/thermal and Verilog simulation analysis, driving silicon debug and continuous improvement initiatives, and mentoring junior engineers. The role requires strong technical expertise in validation, test platform development, scripting, and data analytics, with collaboration across global teams in Boise, Folsom, Hyderabad, and Taiwan.
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Key Responsibilities
- Validation Execution Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment, ensuring on‑schedule starts/completions, risk‑aware re‑plans, and efficient IQP/ETV material usage
- Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time
- Guarantee coverage completeness across MBIST and Native flows; drive Hot/Cold corners, TSV screen/AQLK, async timing boundary coverage, and evidence‑backed closure
- Platform Leadership Develop and debug test programs on SM3/Cobra and Advantest V93K; enforce code quality, reviews, and release discipline
- Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets
- Advanced Analysis, Verilog Simulation & Automation Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes
- Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment
- Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing
- Debug & Continuous Improvement Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root‑cause evidence
- Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning)
- Contribute to DFMEA gap closure and codify 'Definition of Success' for validation quality
- Mentorship & Collaboration Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards
Requirements
- Bachelor’s/Master’s in Electrical or Computer Engineering (or related)
- 8+ years in DRAM/HBM/NAND validation or product engineering
- At least 1 year of HBM Validation experience
- Test platform code development in C/C++, Python, and APG (Algorithmic Pattern Generator)
- Strong expertise in MBIST (SM3/Cobra) or Native Mode (Advantest V93K) testing
- Verilog simulation expertise (bench architecture, stimulus/checkers, waveform/log analysis, correlation to platform behavior)
- Proven ability to execute ValRuns and perform high‑speed I/O validation with eye/IDD characterization
- Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience
- Linux programming experience; familiarity with UVM and version control systems (Git/SVN)
- Comfortable with lab equipment (oscilloscopes, logic analyzers)
- Experience defining CS/QS shmoo targets, async timing boundaries, and coverage‑driven acceptance criteria
- Familiarity with automation and ML‑driven validation workflows (e.g., anomaly classifiers, trend predictors)