About the role
AI summarisedR&D engineer position focused on the design and physical implementation of high-performance System-On-Chip ASICs, involving advanced process nodes and cross-functional team collaboration.
FablessOnsite
Key Responsibilities
- Lead physical design implementation of large ASICs ranging from 500 to 800 million gates.
- Utilize commercial and in-house EDA tools for the design and implementation of integrated circuits in 5nm/3nm/2nm process technologies.
- Collaborate with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.
- Provide technical support to customers and manage customer working relationships.
- Participate in innovation, design flow, and methodology development for deep submicron processes and state-of-the-art ASIC designs.
Requirements
- Master's or PhD in Electrical/Electronics/Computer engineering with 7+ years of relevant experience.
- Proven experience leading physical design implementation for large ASICs (500-800M gates).
- Proficiency with VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, DRC/LVS, STA, and Power Integrity.
- Strong analytical problem-solving skills and cross-functional team collaboration ability.
- Hands-on competency with leading edge physical design EDA tools.
- Experience in Perl, Tcl & Python Scripting languages.