About the role
AI summarisedWe are seeking a Bonding Process Control Engineer responsible for owning, optimizing, and sustaining wafer-level bonding processes, including hybrid wafer-to-wafer bonding, chip-to-wafer bonding, and Temporary Bonding & Debonding (TBDB). This role is critical for enabling next-generation heterogeneous integration and advanced packaging technologies through rigorous process stability, SPC governance, and yield improvement drives.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- Own and maintain SPC control strategies for bonding processes across multiple toolsets.
- Define Critical Process Parameters (CPPs) and Critical Quality Attributes (CQAs) such as alignment accuracy, bond strength, defectivity, warpage, and thickness.
- Drive yield enhancement through structured data analytics, statistical modeling, DOE, and correlation studies.
- Lead root-cause investigations for issues including voids, delamination, alignment offsets, and bonding non-uniformity.
- Diagnose complex process failures involving void formation, debonding, overlay/registration errors, and thermal mismatch.
Requirements
- Bachelor's degree in Materials Science, Chemical, Mechanical, Electrical Engineering, or related fields.
- 3+ years of hands-on experience in wafer bonding, advanced packaging, 3D integration, or related semiconductor process engineering.
- Practical experience with hybrid wafer bonding, direct bonding, and/or Temporary Bonding & Debonding (TBDB) equipment.
- Strong command of SPC, process control methodology, statistical data analysis, DOE, and problem-solving frameworks (e.g., 8D, FMEA).
- Familiarity with bonding-related metrology such as IR inspection, SAM, profilometry, and overlay/alignment metrology.
- Ability to collaborate cross-functionally with process integration, R&D, equipment engineering, and manufacturing teams.