About the role
AI summarisedThe Principal Engineer in NAND Advanced Thin Films Process Development leads the technical strategy and execution for structural and electrical film processes in advanced NAND memory technology. This role involves defining process development roadmaps, leading cross-functional teams, resolving complex technical challenges, mentoring senior engineers, and driving technology transfer from R&D to high-volume manufacturing. The position focuses on enabling next-generation device scaling through innovation in thin film deposition, reliability, yield improvement, and cost reduction.
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Key Responsibilities
- Define and implement the technical strategy for structural and electrical film process development, ensuring alignment with both business and technology objectives
- Lead multi-functional teams in the development, integration, and scaling of thin film processes specifically tailored for advanced NAND structures and devices
- Resolve complex technical challenges that have significant business implications, including root cause analysis and mitigation of process/device failures
- Mentor senior engineers and influence the technical direction throughout the organization, fostering a culture of technical excellence and innovation
- Represent the function in technical forums and participate in strategic collaborations, including industry consortia, technical conferences, and joint development projects
- Deliver solutions that enable and maintain a competitive leadership position in advanced memory technology, including benchmarking against industry standards
- Drive technology transfer and ramp-up activities, ensuring seamless transition from R&D to high-volume manufacturing
- Identify and evaluate emerging trends, risks, and opportunities in structural and electric film technology, providing recommendations for future investments and critical initiatives
- Lead cost reduction, yield improvement, and reliability enhancement programs through innovative process and material utilization
Requirements
- In-depth knowledge of process-device and mechanical interactions, challenges associated with technology/device scaling, and the principles of reliability engineering for next-generation memory nodes
