Micron Technology

Principal/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 6 months ago

About the role

AI summarised

The Principal/Senior Engineer in APTD CEM focuses on developing and deploying post-fab wafer finishing processes for advanced packaging, particularly for high bandwidth memory (HBM) products. The role involves establishing wafer-level process conditions, evaluating new equipment and materials, ensuring quality through measurement and testing, and coordinating cross-functional teams for technology transfer to high-volume manufacturing. This position supports Micron’s innovation in memory technologies by enabling scalable, reliable, and cost-effective advanced packaging solutions.

IDMOnsite

Key Responsibilities

  • Establish and improve wafer level process conditions and technologies (wafer thinning, backside metal interconnect)
  • Upgrade process capabilities and reduce production costs
  • Establish and improve process management projects to deliver technology node requirements and scaling for next node
  • Evaluate and promote new equipment and materials to enhance process capabilities
  • Set up process parameters for a variety of semiconductor equipment
  • Evaluate, promote, and plan for new equipment and materials
  • Ensure defense coverage through process, measurement, inspection, and testing
  • Establish correlations between defense mechanisms to identify improvement opportunities
  • Conduct continuous data analysis to establish advanced controls and identify improvement opportunities
  • Work closely with internal and external partners to build and execute technology development strategies aligned with organizational and business objectives
  • Work closely with various teams, including Package Integration, Assembly Engineering, Front End Wafer Fab, Assembly/Test Engineering, Product Engineering, and Global Quality, to integrate manufacturing processes for optimal performance and quality control

Requirements

  • B.S/M.S./Ph.D. (or equivalent education) in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or other related technical fields
  • 2 or more years of semiconductor process development, preferably in wafer bonding, plating, warpage control and packaging field
  • Proficiency in Python, R, SQL for statistical analysis, process modeling, and data analytics.
  • Experience with Visual Basic for automation and tool integration.