A*STAR

Senior /Lead Research Engineer (FOWLP/2.5D/3D package integration) (HI), IME

A*STAR
ResearchSingaporeOnsitePosted 3 weeks ago

About the role

AI summarised

The Advanced Packaging Program at the Institute of Microelectronics (IME) seeks a passionate Scientist or Senior Scientist to drive state-of-the-art advanced packaging platform technologies, including 2.5D/3D IC and Co-packaged optics. This pivotal role involves developing critical modules for heterogeneous integration of chiplets in a dynamic, collaborative research environment.

ResearchOnsiteInstitute of Microelectronics

Key Responsibilities

  • Develop advanced packaging technology platforms (fan-out packaging, 2.5D interposer, and 3D stacking) capabilities and novel process integration approaches for heterogeneous chiplets integration.
  • Establish design rules and PDK in collaboration with design and process module teams for advanced packaging technologies.
  • Lead capability development projects for internal and external industry projects involving new materials, advanced process integration, and test vehicle designs.
  • Collaborate with cross-functional teams (design, unit process, yield improvement) and external partners to define technology roadmaps and identify gaps.
  • Manage customer/partner engagement, including presenting technical content to senior stakeholders and driving joint development projects.
  • Mentor junior engineers and students in semiconductor technology, contributing to workforce development.

Requirements

  • Bachelor's or Master's in Materials Science & Engineering, Mechanical, Chemical, Electronics/Electrical & Computer Engineering, Physics, Chemistry, or a closely related field.
  • 5-10 years of semiconductor experience with expertise in Cu backend integration and exposure to advanced packaging technologies (flip-chip, FOWLP, 2.5D/3D, TSV, hybrid/fusion bonding).
  • Proven ability to work effectively in a diverse, matrixed environment and collaborate cross-functionally.
  • Strong analytical and problem-solving skills, including proficiency with DOE and SPC (JMP/Minitab).
  • NPI to HVM ramp experience, including process window definition and yield/cost improvement through pilot to high-volume manufacturing.
  • Reliable understanding of JEDEC/IPC/JESD standards and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX).
  • Excellent written and verbal communication abilities.
  • Demonstrated ability to manage multiple projects and priorities in a research and translational setting.