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STMicroelectronics

Intern, IC Digital Design (Front-end)

STMicroelectronics
Integrated Device ManufacturingSingapore, SingaporeOnsitePosted 4 months ago
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About the role

AI summarised

This internship role involves supporting the digital design team in enhancing and automating design verification flows, with a focus on memory built-in self-test (MBIST) packaging, front-end verification tasks (linting, CDC, RDC), and Spyglass CDC netlist flow setup. The intern will develop scripts and automation tools, collaborate with cross-functional teams, and gain hands-on experience with industry-standard EDA tools in a semiconductor environment.

IDMOnsiteDigital Design Front-End

Key Responsibilities

  • Design and implement a new membox packaging flow for generic MBIST, ensuring modularity and reusability across different memory instances
  • Collaborate with memory IP teams to understand requirements and optimize the packaging flow for efficiency and scalability
  • Prepare Lint, CDC, and RDC verification tasks into a standalone kit
  • Integrate and validate the recital flow within the design kit to ensure seamless operation and compliance with design standards
  • Establish and configure a CDC netlist flow using Synopsys Spyglass to detect and analyze clock domain crossing issues
  • Automate the generation and verification of CDC reports to support timely design sign-off
  • Develop scripts and automation tools to streamline various digital design verification flows, improving productivity and reducing manual intervention
  • Troubleshoot and debug flow issues, providing timely solutions to support design teams
  • Work closely with cross-functional teams including design, verification, and EDA tool experts to align flow development with project goals

Requirements

  • Able to commit minimum 8 months of internship
  • Pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Strong fundamentals in digital logic design and hardware design principles
  • Proficiency in Verilog or System Verilog for digital design and verification
  • Programming or scripting skills in Python, plus at least one of: C/C++, System Verilog, TCL, or Shell
  • Familiarity with Synopsys tools such as Spyglass, Design Compiler, or similar linting and CDC analysis tools
  • Ability to analyze technical data and generate concise reports
  • Experience or coursework in VLSI/ASIC design or verification
  • Exposure to formal verification, linting, or CDC tools
  • Interest in EDA tool evaluation and design methodology research
  • Strong curiosity about improving engineering workflows
  • Good communication skills to collaborate effectively with cross-functional teams
  • Self-motivated and eager to learn new tools, methodologies, and industry best practices
  • Ability to work independently as well as in a team-oriented environment