About the role
AI summarisedThe Advanced Packaging Program at the Institute of Microelectronics (IME) seeks a passionate Senior Scientist to drive cutting-edge research and development in advanced package assembly for heterogeneous integration. This pivotal role focuses on scaling up chip-to-wafer/chip-to-chip fine pitch micro-bump thermal compression bonding and fusion/hybrid bonding technologies.
ResearchOnsiteInstitute of Microelectronics
Key Responsibilities
- Lead flip chip bonding process capabilities development to scale down micro bump bonding and chip-to-wafer hybrid bonding technologies for heterogeneous chiplets integration.
- Develop assembly process integration approaches to realize complex novel system-in-package architectures by integrating chiplets.
- Establish assembly process design rules in collaboration with design and wafer process integration teams for advanced packaging platform technologies.
- Identify capability needs for future package architectures to conceptualize and lead assembly development projects involving new materials and innovative concepts.
- Serve as a Subject Matter Expert (SME) for internal and external stakeholders, providing technical guidance and leading project execution.
- Collaborate with cross-functional teams (design, yield improvement, external partners) to define technology roadmaps and identify gaps.
- Develop new Intellectual Properties (IPs) and strengthen the advanced packaging IP portfolio in assembly processes.
- Mentor junior engineers and students in semiconductor technology, contributing to workforce development.
Requirements
- PhD in Materials Science & Engineering, Mechanical, Chemical, Electronics/Electrical & Computer Engineering, Physics, Chemistry, or a closely related field.
- 5-10 years of experience in the semiconductor industry with expertise in package assembly processes.
- Proven exposure to advanced package assembly technologies including thermal compression bonding, chip-to-wafer bonding, and underfilling.
- Strong analytical and problem-solving skills (e.g., Ishikawa, DOE, SPC using JMP/Minitab).
- Experience with NPI to HVM ramp, including process window definition and yield/cost improvement.
- Working knowledge of reliability standards such as JEDEC/IPC/JESD and failure analysis flows (X-ray, FIB/SEM-EDX).
- Excellent written and verbal communication abilities for technical presentations.
- Demonstrated ability to manage multiple projects in a research and translational environment.