About the role
AI summarisedSenior/Lead Research Engineer responsible for owning, optimizing, and sustaining wafer-level bonding processes at IME, a semiconductor R&D institute. The role focuses on process stability, SPC governance, yield improvement, defect reduction, and robust process-control strategies for advanced packaging technologies.
ResearchFull-timeInstitute of Microelectronics
Key Responsibilities
- Own and maintain SPC control strategies for bonding processes across multiple toolsets.
- Define Critical Process Parameters (CPPs) and Critical Quality Attributes (CQAs) such as alignment accuracy, bond strength, defectivity, warpage, and thickness.
- Establish and optimize control limits, reaction plans, and process windows to ensure process robustness and manufacturability.
- Drive yield enhancement through structured data analytics, statistical modeling, DOE, and correlation studies.
- Lead root‑cause investigations for issues such as voids, delamination, alignment offsets, particle‑induced defects, and bonding non‑uniformity.
- Implement systematic defect‑reduction strategies and corrective actions.
- Serve as the process owner for bonding toolsets, including recipe setup, qualification, matching, and continuous improvement.
- Execute tool health monitoring, run‑to‑run control, and equipment baseline management.
- Collaborate with equipment engineering to enable uptime, stability, and PM efficiency.
- Work closely with process integration, R&D, equipment engineering, manufacturing, and quality teams to achieve product ramps, technology transfers, and new capability development.
- Support development builds, engineering lots, and technology bring‑up activities.
- Diagnose complex process failures involving void formation, debonding, overlay/registration errors, thermal mismatch, and stress‑related defects.
Requirements
- Bachelor's degree in Materials Science, Chemical, Mechanical, Electrical Engineering, or related fields.
- 3+ years of hands‑on experience in wafer bonding, advanced packaging, 3D integration, or related semiconductor process engineering.
- Process & Tool Expertise
- Practical experience with hybrid wafer bonding, direct bonding, and/or Temporary Bonding & Debonding (TBDB) equipment.
- Familiarity with bonding‑related metrology such as IR inspection, SAM, profilometry, bond‑strength measurement, overlay/alignment metrology, and thickness mapping.
- Data & Statistical Skills
- Strong command of SPC, process control methodology, statistical data analysis, DOE, and problem‑solving frameworks (e.g., 8D, FMEA).
- Experience in high‑volume manufacturing or advanced packaging R&D environments is a strong plus.