Micron Technology

Principal Engineer, (NAND Cell Film Process)

Micron Technology
Integrated Device ManufacturingSingapore, SingaporeFull-time4 months ago

About the role

AI summarised

Principal Engineer leading cell film process development for advanced NAND memory technology at Micron, a semiconductor industry leader. Responsible for defining technical strategy, driving innovation in thin film deposition (ALD, CVD), and ensuring successful integration into high-volume manufacturing.

IDMFull-timeSTPG

Key Responsibilities

  • Define and implement the technical strategy for cell film process development, ensuring alignment with both business and technology objectives.
  • Lead multi-functional teams in the development, integration, and scaling of thin film processes specifically tailored for advanced NAND devices.
  • Oversee the end-to-end development of process modules, with a strong focus on manufacturability, scalability, and readiness for integration.
  • Resolve complex technical challenges that have significant business implications, including root cause analysis and mitigation of process/device failures.
  • Mentor senior engineers and influence the technical direction throughout the organization, fostering a culture of technical excellence and innovation.
  • Represent the function in technical forums and participate in strategic collaborations, including industry consortia, technical conferences, and joint development projects.
  • Deliver solutions that enable and maintain a competitive leadership position in advanced memory technology, including benchmarking against industry standards.
  • Drive technology transfer and ramp-up activities, ensuring seamless transition from R&D to high-volume manufacturing.
  • Identify and evaluate emerging trends, risks, and opportunities in cell film technology, providing recommendations for future investments and critical initiatives.
  • Lead cost reduction, yield improvement, and reliability enhancement programs through innovative process and material utilization.

Requirements

  • PhD or equivalent degree in Materials Science, Chemical Engineering, Physics, Chemistry, Electrical Engineering, or a related field.
  • 5-10 years of experience in Thin Film research and development for NAND process, specifically including Diffusion, CVD, and Cell Films.
  • Demonstrated mastery of thin film deposition processes, including Atomic Layer Deposition and Chemical Vapor Deposition, encompassing process design, optimization, and integration for high-density NAND applications.
  • In-depth knowledge of process-device interactions, challenges associated with device scaling, and the principles of reliability engineering for next-generation memory nodes.
  • Proven track record of developing and implementing novel chemistries, materials, and hardware solutions, such as chamber design, plasma source optimization, and gas delivery systems.
  • Expertise in advanced characterization techniques, such as X-ray Reflectivity (XRR), ellipsometry, Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), Secondary Ion Mass Spectrometry (SIMS), and X-ray Photoelectron Spectroscopy (XPS), as well as electrical evaluation methods (including leakage, impedance, capacitance, and breakdown analysis).
  • Strong foundation in device physics, including Metal-Oxide Capacitor (MOCAP), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and 3D NAND operation, with an ability to analyze structural-process correlations and conduct failure analysis.
  • Experience in benchmarking technology, conducting competitive analyses, and assessing industry trends, with the capability to translate complex data into actionable technology roadmaps and process improvements.
  • Ability to lead cross-disciplinary teams in the development and deployment of new process technologies, including collaboration with integration, device, reliability, and manufacturing engineering groups.
  • Proficiency in statistical process control (SPC), design of experiments (DOE), and data analytics for process optimization and fixing.
  • Experience with regulatory compliance, intellectual property management, and technical documentation in a semiconductor manufacturing environment.