About the role

AI summarised

Seeking a Staff Packaging SI Engineer to perform advanced electromagnetic and signal integrity simulations on IC Packages and PCBs, optimizing electrical performance for high-speed interfaces like DDR and SerDes channels.

FablessOnsite

Key Responsibilities

Perform electromagnetic extractions on interconnects in IC Packages and PCBs using tools like Ansys HFSS, Q3D, SIWave.
Conduct signal integrity circuit simulations for parallel digital interfaces (DDR), analog SerDes channels, and Power Delivery Networks (PDN) using ADS, Ansys Designer, or HSpice.
Collaborate with IC Package Design engineers on electrical design optimization of Packaging Interconnects and PDN.
Work with IP owners, chip leads, package, and PCB design engineers to optimize Bump/Ball maps and verify electrical performance against system targets.
Perform frequency and time domain lab measurements on silicon die, substrates, PCBs, and systems using micro probe stations.
Contribute to the documentation of simulation/extraction flows and Design Guidelines.
Interface with substrate and assembly suppliers to drive packaging technology improvements for electrical performance, including 2.5D Integration.

Requirements

MS in EE with 6+ years of experience OR Ph.D. in EE with 3+ years of experience OR BS in EE with 8+ years of experience in Signal Integrity / Power Integrity Analysis and Interconnect Design Optimization.
Solid knowledge in Interconnect Electromagnetics, Transmission Line Theory, and Circuit Theory.
Power user proficiency in Ansys HFSS, Q3D, SIWave and/or Cadence Sigrity Power SI.
Power user proficiency in Ansys Designer, HSpice, or Agilent ADS.
Hands-on lab measurement experience with VNA, TDR System & Oscilloscopes, preferably with micro-probe stations.
Working knowledge of Cadence APD and AutoCAD.
Strong communication, analytical, and organizational skills with meticulous attention to detail.