About the role
AI summarisedApplied Materials seeks a senior Yield Development Engineer to drive yield learning and ramp for advanced semiconductor and photonic devices, transitioning from R&D to high-volume manufacturing. The role involves identifying yield limiters, executing DOEs, analyzing data, and collaborating with cross-functional teams to establish robust processes.
EquipmentFull-timeEngineering
Key Responsibilities
- Lead yield development activities across early technology development, pilot runs, and high‑volume manufacturing ramp.
- Identify, analyze, and eliminate yield limiters related to process variation, integration interactions, and design sensitivities.
- Define and execute yield-focused DOEs to characterize process windows, sensitivity drivers, and defect mechanisms.
- Perform detailed yield data analysis, including parametric, inline, defect, and final test data, to guide process improvements.
- Collaborate with process integration and module teams (lithography, etch, deposition, CMP, metrology) to close yield gaps.
- Drive root-cause analysis for systematic and random yield loss using statistical, physical, and failure analysis methods.
- Provide feedback to design teams on DFM / DfY (Design for Yield) opportunities and layout-related yield risks.
- Support technology transfer to high-volume manufacturing, ensuring yield performance meets business requirements.
- Establish yield monitoring strategies, control plans, and baseline metrics for sustained manufacturing performance.
- Contribute to yield ramp strategies and technology roadmaps, balancing performance, cost, and manufacturability.
- Mentor junior engineers and technicians on yield analysis tools, methodologies, and best practices.
Requirements
- Master's degree or PhD in Electrical Engineering, Chemical Engineering, Materials Science, or a related field (PhD preferred).
- Minimum 5 years of industry experience, with 3+ years in yield development, process integration, or manufacturing yield engineering, preferably in high‑volume semiconductor environments.
- Strong understanding of semiconductor fabrication processes and their impact on yield (lithography, etch, deposition, metrology).
- Demonstrated expertise in statistical yield analysis and process control, including DOE, SPC, JMP, and multivariate analysis.
- Experience correlating inline, defect, electrical, and optical test data to yield performance.
- Ability to read and interpret layout data (GDS, OASIS); familiarity with OPC and layout-related yield effects is a strong plus.
- Knowledge of photonics devices, optical components, and optical test methodologies is desirable.
- Strong communication skills with the ability to clearly present yield results and recommendations to cross‑functional and senior stakeholders.
- Highly organized and detail‑oriented, capable of managing multiple yield improvement efforts in parallel.
- Familiarity with semiconductor manufacturing standards and best practices (ISO, SEMI, ITAR) and basic project management skills are a plus.